1. Field of the Invention
The present invention relates to a driving circuit used in a display apparatus and a liquid crystal display apparatus using such a driving circuit, and in particular to a planar display apparatus, especially, an active matrix liquid crystal display apparatus for displaying an image having multiple gray-scale levels and a driving circuit used in the same.
2. Description of the Related Art
The conventional oscillating voltage method will be described. The conventional oscillating voltage method is disclosed in Japanese Laid-Open Patent Publication No. 6-27900 (Japanese Patent Publication No. 7-7248) which is assigned to the same assignee with the present invention. The oscillating voltage method is used in a display apparatus in order to display an image having multiple gray-scale levels. The display apparatus includes a matrix display panel which has a plurality of pixels arranged in a matrix. The image formation is performed by supplying each of the pixels with a scanning voltage (gate voltage) and a driving voltage corresponding to display data having gray-scale information. In detail, a driving voltage having an oscillating component is sent to a source line (signal line) and then transmitted through an electric circuit acting as a low-pass filter. As a result, an average voltage obtained by suppressing the oscillating component of the driving voltage is applied to each of the pixels. The pixel which is supplied with the average voltage has been scanned in one scanning period by a scanning voltage. Accordingly, the average voltage supplied to the pixel corresponds to a gray scale level of the display data in one scanning period. In this manner, multiple gray-scale display is performed.
A liquid crystal display panel includes a plurality of source lines and a plurality of pixels. The resistance components and the capacitance components of the source lines and the pixels act as a low-pass filter. In the case where a storage capacitor is provided, the liquid crystal capacitance components and the storage capacitance components of the source lines and the pixels also act as a low-pass filter together with the resistance components and the capacitance components thereof. In other words, such components average the driving voltage having an oscillating component sent to each source line. Accordingly, a constant voltage is applied to the pixels. The resistance components and the capacitance components of the pixel selected by the scanning voltage in one scanning period and the source line connected to such a pixel act as a load for an output circuit. In this specification, such a source line and a pixel are referred together simply as a "load".
With reference to FIGS. 13 and 14, a conventional 3-bit driving device used in a liquid crystal display apparatus will be described. FIG. 13 shows a configuration of one of a plurality of output circuits (output circuit 500a) contained in a 3-bit digital driving device 500 configured as an LSI, and FIG. 14 schematically shows a configuration of a selection control section 530 in relation with the other components of the 3-bit driving device 500.
The 3-bit driving device 500 is used for driving a liquid crystal display panel in a liquid crystal display apparatus using the oscillating voltage method. As is shown in FIG. 14, the 3-bit driving device 500 includes a plurality of output circuits each provided for a source line (load) of the liquid crystal display panel. The 3-bit driving device 500 further includes voltage supply lines 10, 12, 15 and 17 respectively for supplying reference gray-scale voltages V0, V2, V5 and V7 sent from outside the 3-bit driving device 500 to the output circuits. The voltage supply lines 10, 12, 15 and 17 are respectively connected to voltage input terminals 1 through 4 provided at an end of the 3-bit driving device 500.
The output circuit 500a shown in FIG. 13, which is one of such output circuits, outputs gray-scale voltages based on data signals D0, D1 and D2 forming 3-bit display data to the corresponding source lines. The output circuit 500a includes a sampling circuit 510 for sampling the data signals D0, D1 and D2 based on a control signal Tsmp, a holding circuit 520 for storing an output from the sampling circuit 510 using a control signal LS, and a selection control section 530 for outputting a gray-scale voltage having a prescribed level, based on memory data d0 through d2 stored in the holding circuit 520.
As is shown in FIG. 14, the selection control section 530 includes a switch section 530b having four analog switches ASW0, ASW2, ASW5, and ASW7 respectively connected to the voltage supply lines 10, 12, 15 and 17, and a selection control circuit 530a for closing and opening the analog switches ASW0, ASW2, ASW5 and ASW7 based on the memory data d0, d1 and d2 stored in the holding circuit 520 and selecting two prescribed reference gray-scale voltages among the four reference gray-scale voltages V0, V2, V5 and V7.
The selection control circuit 530a is supplied with memory data d0 through d2 and a signal T3 shown in FIG. 15 having a duty ratio of 2:1. The memory data d0 through d2 and the signal T3 are used for the above-mentioned switching of the analog switches ASW0, ASW2, ASW5 and ASW7.
The conventional 3-bit driving device 500 having the above-described structure operates in the following manner.
Table 1 shows a logic configuration of the selection control circuit 530a, namely, the relationship between input and output.
TABLE 1 ______________________________________ Display data Output from the selection Decimal control circuit number d2 d1 d0 S0 S2 S5 S7 ______________________________________ 0 0 0 0 1 1 0 0 1 .tau.3 .tau.3 2 0 1 0 1 3 0 1 1 .tau.3 .tau.3 4 1 0 0 .tau.3 .tau.3 5 1 0 1 1 6 1 1 0 .tau.3 .tau.3 7 1 1 1 1 ______________________________________
In Table 1; 3-bit display data, which is to be sent to the selection control circuit 530a, is formed of memory data d0, d1 and d2. Signals s0, s2, s5 and s7, which are output from the selection control circuit 530a, are control signals respectively for the analog switches ASW0, ASW2, ASW5 and ASW7. Symbol .tau.3 indicates a value which becomes "1" when the signal T3 is "high" and becomes "0" when the signal T3 is "low". Symbol .tau.3 indicates a value which becomes "1" when the signal T3 is low and becomes "0" when the signal T3 is high. The blank columns indicate that the control signal is "0".
For example, when the value of the display data is 1 (d2=0, d1=0, d0=1), the control signal s0 has a waveform obtained by inverting the waveform of the signal T3, and the control signal s2 has the same waveform as that of the signal T3. In the case that the analog switches ASW0, ASW2, ASW5 and ASW7 are controlled to be "ON" when the control signals s0, s2, s5 and s7 are "high" respectively, a signal for selecting the reference gray-scale voltages V0 and V2 having a duty ratio of 1:2 is obtained as is shown in waveform (a) in FIG. 16.
By setting the cycle of the waveform (a), namely, the cycle of the signal T3 to be sufficiently shorter than the cycle of the cut-off frequency of a low-pass filtering function of the liquid crystal display panel, a DC voltage which has an average value of the oscillating voltages is provided to pixels.
Waveforms (b), (c) and (d) respectively correspond to the outputs from the output circuit 500a when the values of the display data are 3, 4, and 6. Table 2 shows the relationship between the display data sent to the 3-bit driving device 500 and the output from the 3-bit driving device 500.
TABLE 2 ______________________________________ Display data Output from Decimal the driving device number D2 D1 D0 V ______________________________________ 0 0 0 0 V.sub.0 1 0 0 1 1 #STR1## 2 0 1 0 V.sub.2 3 0 1 1 2 #STR2## 4 1 0 0 3 #STR3## 5 1 0 1 V.sub.5 6 1 1 0 4 #STR4## 7 1 1 1 V.sub.7 ______________________________________
Hereinafter, how a current flows in the 3-bit driving device 500 when the oscillating voltages are applied will be described. In the following explanation, the value of the display data is 1.
FIG. 17 illustrates a detailed waveform of the output from the 3-bit driving device 500 shown as waveform (a) in FIG. 16 when the reference gray-scale voltages have the relationship of V0&gt;V2. In FIG. 17, the rightward arrow (Iv0) indicates the direction of the current flowing from the 3-bit driving device 500 to the load. The leftward arrow (Iv2) indicates the direction of the current flowing from the load to the 3-bit driving device 500.
In time duration T1 during which the reference gray-scale voltage V0 is output, the load has a potential lower than that of the reference gray-scale voltage V0 after a transition period. Thus, the current Iv0 flows from the voltage supply line 10 to the load through the analog switch ASW0 (FIG. 14). Where the "ON" resistance of the analog switch ASW0 is rON, the total resistance between the output terminal of the 3-bit driving device 500 and the pixel electrode is RL, and the potential of the pixel is Vp, the level of the current Iv0 is: EQU .vertline.Iv0.vertline.=(V0-Vp)/(rON+RL).
In time duration T2 in which the reference gray-scale voltage V2 is output, the load has a potential higher than that of the reference gray-scale voltage V2. Thus, the current Iv2 flows from the load to the voltage supply line 12 through the analog switch ASW2 (FIG. 14). The level of the current Iv0 is: EQU .vertline.Iv2.vertline.=(Vp-V2)/(rON+RL).
When a sufficient length of time has passed after a prescribed oscillating voltage is applied to the load, the potential of the pixel is: EQU Vp=(V0+2.times.V2)/3.
Accordingly, .vertline.Iv0.vertline.=2.times..vertline.Iv2.vertline..
In consideration of the voltage drop caused by the resistance, the circulation theory needs to be considered to obtain the potential Vp of the pixel from a mathematical point of view. However, since the gist of the present invention is not in presenting a mathematically precise proof, detailed explanation on how to find such a precise potential of the pixel will be omitted here.
In a driving device used in practice, the output circuit 500a shown in FIG. 13 is required for each of a plurality of source lines of the liquid crystal display panel. In order to drive a VGA type display panel, for example, 1920 output circuits are necessary. It is not practical to provide such a large number of circuits in one driving device. Accordingly, for example, 16 driving devices each including 120 circuits are used to drive one liquid crystal display panel. In each of such driving devices, each reference gray-scale voltage is supplied to the corresponding analog switch of the output circuits through the voltage supply line.
FIG. 18 shows how the reference gray-scale voltage V0 supplied by the voltage supply line 10 and the reference gray-scale voltage V2 supplied by the voltage supply line 12 are sent from the input terminals 1 and 2 of the driving device to the load through the analog switches ASW0 and ASW2.
The voltage supply lines 10 and 12 each have a resistivity .rho.. Distance L0(i) between the input terminal 1 and the output circuit corresponding to the "i"th load (hereinafter, referred to as the "i"th output circuit) 500i is equal to distance L2(i) between the input terminal 2 and the "i"th output circuit 500i. Accordingly, the distances L0(i) and L2(i) will be collectively referred to simply as L(i), hereinafter.
Referring to FIG. 18, the resistance between the input terminal 1 or 2 and the "i"th output circuit 500i is .rho..multidot.L(i). Accordingly, a voltage drop occurs in the voltage supply line 10 by the current Iv0(i) flowing between the "i"th output circuit 500i and the "i"th load, and a voltage rise occurs in the voltage supply line 12 by the current Iv2(i) flowing between the "i"th output circuit 500i and the "i"th load.
Where the voltages at the input terminals 1 and 2 are respectively V0(0) and V2(0), the voltages V0(i) and V2(i) at the positions which are away from the input terminals 1 and 2 by distance L(i) are: EQU V0(i)=V0(0)-.rho..multidot.L(i).vertline.Iv0(i).vertline. EQU V2(i)=V2(0)+.rho..multidot.L(i).vertline.Iv2(i).vertline..
Accordingly, the potential of the pixel is expressed by is the following equation. ##EQU1##
From the above-described principle, EQU .vertline.Iv0(i).vertline.=2.multidot..vertline.Iv2(i).vertline..
By substituting this into the above equation, ##EQU2## is obtained.
This indicates that, in consideration of only the "i"th output circuit, the phenomenon does not occur that the voltage supplied to the "i"th load changes by the influence of the current which flows to the output circuit to drive the "i"th load.
Accordingly, in the case that an oscillating voltage corresponding to the display data 1 (interpolation gray-scale voltage) is supplied through all the output terminals of the driving device 500, the currents flowing to all the output circuits for driving the respective loads provide all the loads, namely, all the pixels with a uniform voltage.
In the case that the output circuits corresponding to two adjacent source lines (loads) respectively output the display data 1 and 3, the driving device 500 operates in the following manner.
FIG. 19 shows waveforms of the voltages of the outputs from the driving device 500. Between the output circuit outputting the display data 1 and the corresponding load, the current Iv0 flows through the voltage supply line 10 and the current Iv2 flows through the voltage supply line 12. Between the output circuit outputting the display data 3 and the corresponding load, the current Iv2' flows through the voltage supply line 12 and the current Iv5 flows through the voltage supply line 15.
The currents Iv2 and Iv2' flow in opposite directions to each other. In other words, the current Iv2 which is caused by an oscillating voltage corresponding to the display data 1 and is to cause a voltage rise in the voltage supply line 12 is counteracted by the current Iv2' caused by an oscillating voltage corresponding to the display data 3.
In the case when the difference between the reference voltages V0 and V2 is substantially equal to the difference between reference voltages V2 and V5, the current Iv2 and Iv2' have almost the same absolute value and flow in opposite directions to each other. As a consequence, no voltage drop or voltage rise occurs in the voltage supply line 12 which supplies the reference gradation voltage V2.
However, a voltage drop occurs in the voltage supply line 10 which supplies the reference gradation voltage V0 with certainty. Therefore, the counteraction between the current flowing from the output circuit and the current flowing to the output circuit does not occur, and thus a change in the voltage supplied to the pixel is not compensated for. As a result, a gray-scale voltage Vp1 (interpolation gray-scale voltage; corresponding to the display data 1) supplied to the pixel is lowered.
FIGS. 20A and 20B illustrate the relationship between the reference gray-scale voltages V0 and V2 and the distance by which the currents Iv0 and Iv2 flow from the input terminals 1 and 2 of the voltage supply lines 10 and 12. A change in the voltage V1 (interpolation gray-scale voltage) applied to the pixels when the value of the display data is 1 with respect to the distance is also shown. FIG. 20A illustrates such relationship when all the outputs from the driving device 500 correspond to the display data 1. FIG. 20B illustrates such relationship when the outputs from two adjacent output circuits of the driving device 500 correspond to the display data 1 and 3 respectively.
In the case where all the outputs from the driving device 500 correspond to the display data 1, as is shown in FIG. 20A, the voltage V1 applied to the pixels is constant regardless of the distance.
In the case where the outputs from two adjacent output circuits of the driving device 500 correspond to the display data 1 and 3 respectively, as is shown in FIG. 20B, the voltage V1 applied to the pixels corresponding to the display data 1 decreases as the distance increases. The voltage V1 at distance x is lower than the voltage V1 at the input terminal by .DELTA.V1.
In the output circuit outputting the display data 3, the current Iv2' which is to cause a voltage drop is counteracted by the current Iv2, and thus no voltage drop occurs in the voltage supply line 12 for supplying the reference voltage V2. In the voltage supply line 15 for supplying the reference voltage V5, a voltage rise occurs by the current Iv5. As a result, the resultant voltage corresponding to the display data 3 at distance x is higher than the voltage at the input terminal.
In the above explanation, the reference gray-scale voltages have the relationship of V0&gt;V2&gt;V5 (&gt;V7). The voltage to be supplied to the pixels changes in the same manner when the relationship of the reference gray-scale voltages is V0&lt;V2&lt;V5 (&lt;V7).
In the above explanation, some of the conditions are simplified. Such conditions will be described additionally, hereinafter.
In practice, the current flowing in each output circuit is one current component of the entire current which flows in each of the voltage supply lines. In the above explanation, a voltage drop or a voltage rise in the "i"th output circuit is regarded as the sum of voltage drops or the voltage rises which are caused between the input terminal of each voltage supply line and the connection point of the voltage supply line and the "i"th output circuit.
Needless to say, for example, the current component in the "i-1"th output circuit causes a voltage drop or a voltage rise only between the input terminal of the voltage supply line and the connection point of the voltage supply line and the "i-1"th output circuit.
In the above description, each voltage supply line has an input terminal only at one end thereof. In practice, each voltage supply line often has an input terminal at both ends thereof. In such a case, analysis on the current is more complicated. The other conditions which are simplified in the above explanation are not directly related to the present invention and thus detailed explanation thereof will be omitted.
A conventional 6-bit driving device will be described.
FIG. 21 shows a configuration of one output circuit 600a of a 6-bit driving device 600. The output circuit 600a corresponds to one source line (load), and includes a sampling circuit 610 for sampling data signals D0 through D5 forming 6-bit display data based on a sampling signal Tsmp, a holding circuit 620 for storing an output from the sampling circuit 510, and a selection control section 630 for controlling a plurality of analog switches ASW8i (i=0, 1 . . . 8) based on memory data d0 through d5 in the holding circuit 620.
The selection control section 630 includes a switch section 630b having a plurality of analog switches ASW8i, and a selection control circuit 630a for controlling the plurality of analog switches ASW8i based on the memory data d0 through d5. Reference gray-scale voltages V8i (i=0, 1, . . . 8) are supplied to the switch section 630b from outside the 6-bit driving device 600 and output to the load through the respective analog switches ASW8i.
FIG. 22 shows a detailed configuration of the selection control circuit 630a. As is shown in FIG. 22, the selection control circuit 630a includes an interpolation signal generation circuit 631 and a voltage selection and modulation circuit 632. The selection control circuit 630a is supplied with four signals t1 through t4 respectively having duty ratios of 7:1, 6:2, 5:3 and 4:4 as are shown in FIG. 23. The interpolation signal generation circuit 631 forms eight signals having waveforms which respectively have duty ratios of 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6 and 1:7 based on the four signals t1 through t4 and selects a prescribed signal among the eight signals based on the lower 3 bits d0, d1 and d2 of the 6-bit display data. The selected signal is output as an interpolation signal T.
The voltage selection and modulation circuit 632 controls the analog switches ASW8i based on the upper 3 bits d3 through d5 of the 6-bit display data and selects voltages forming pairs among the nine reference gray-scale voltages. The voltage selection and modulation circuit 632 further modulates the selected pair of voltages using the interpolation signal T generated by the interpolation signal generation circuit 631.
Table 3A shows a logical configuration of the interpolation signal generation circuit 631, and Table 3B shows a logical configuration of the voltage selection and modulation circuit 632.
TABLE 3A ______________________________________ d2 d1 d0 T ______________________________________ 0 0 0 1 0 0 1 .tau.1 0 1 0 .tau.2 0 1 1 .tau.3 1 0 0 .tau.4 1 0 1 .tau.3 1 1 0 .tau.2 1 1 1 .tau.1 ______________________________________
TABLE 3B ______________________________________ d5 d4 d3 S0 S8 S16 S24 S32 S40 S48 S56 S64 ______________________________________ 0 0 0 T T 0 0 1 T T 0 1 0 T T 0 1 1 T T 1 0 0 T T 1 0 1 T T 1 1 0 T T 1 1 1 T T ______________________________________
The interpolation signal T from the interpolation signal generation circuit 631 is expressed by: EQU T=(0)+(1).tau..sub.1 +(2).tau..sub.2 +(3).tau..sub.3 +(4).tau..sub.4 +(5).tau..sub.3 +(6).tau..sub.2 +(7).tau..sub.1
where numerical figures in parentheses ( ) are decimal numbers of the display data.
For example, when the display data is 4, (d2, d1, d0)=(1,0,0). Accordingly, the interpolation signal generation circuit 631 selects the signal t4 based on Table 3A, and sends the signal t4 to the voltage selection and modulation circuit 632 as an interpolation signal T.
Since (d5, d4, d3)=(0,0,0), the voltage selection and modulation circuit 632 selects the control signals s0 and s8 of the analog switches ASW0 and ASW8 corresponding to the reference gray-scale voltages V0 and V8 and modulates the signals s0 and s8 using the signal t4 and a signal t4 obtained by inverting the signal t4. In other words, the control signal s0 has the same waveform as the signal t4, and the control signal s8 has a waveform obtained by inverting the waveform of the signal t4.
Accordingly, the 6-bit driving device 600 outputs a signal having a waveform shown in FIG. 24. Based on the above-described principle, the pixels are supplied with a DC voltage which is an average voltage of the oscillation voltages.
In this manner, seven interpolation gray-scale voltages are formed between the nine reference gray-scale voltages. As a result, 64-gray-scale display is realized by the 6-bit driving device 600.
However, in the state where the output circuits close to each other output oscillating voltages (interpolation gray-scale voltage) which are formed by a pair of adjacent reference gray-scale voltages, the voltage to be supplied to the pixels changes as in the case of a 3-bit driving device. As a result, accurate gray-scale levels are not obtained.
FIG. 25 shows waveforms of an interpolation gray-scale voltage V5 between the reference gray-scale voltages V0 and V8 and an interpolation gray-scale voltage V11 between the reference gray-scale voltages V8 and V16. In this case, a voltage drop occurs in a voltage supply line for supplying the reference gray-scale voltage V0 by the current Iv0 which flows to the load. However, a normal voltage rise for compensating for such a voltage drop does not occur in a voltage supply line for supplying the reference gray-scale voltage V8 by the influence of a current Iv8' for generating the interpolation gray-scale voltage V11 which flows to the load. As a result, the interpolation gray-scale voltage V5 to be supplied to the pixels changes.
In a voltage supply line for supplying a reference gray-scale voltage V16, a voltage rise occurs; but in a voltage supply line for supplying the reference gray-scale voltage V8, a normal voltage drop does not occur. As a result, the interpolation gray-scale voltage V11 to be supplied to the pixels also changes.
A conventional 8-bit driving device will be described.
FIG. 26 shows a configuration of one output circuit 700a of an 8-bit driving device 700. The output circuit 700a corresponds to one source line (load), and includes a sampling circuit 710 for sampling data signals D0 through D7 forming 8-bit display data based on a sampling signal Tsmp, a holding circuit 720 for storing an output from the sampling circuit 710, and a selection control section 730 for controlling a plurality of analog switches ASW32i (i=0, 1 . . . 8) based on memory data d0 through d5 in the holding circuit 720.
FIG. 27 shows a configuration of the selection control section 730. The selection control section 730 includes a switch section 730b having the plurality of analog switches ASW32i, and a selection control circuit 730a for controlling the analog switches ASW32i based on the memory data d0 through d7 in the holding circuit 720. Reference gray-scale voltages V32i (i=0, 1, . . . 8) are supplied to the switch section 730b from outside the 8-bit driving device 700 and output to the load through the respective analog switches ASW32i.
FIG. 28 shows a detailed configuration of the selection control circuit 730a. As is shown in FIG. 28, the selection control circuit 730a includes an interpolation signal generation circuit 731 and a voltage selection and modulation circuit 732. The interpolation signal generation circuit 731 selects a prescribed signal among a plurality of signals having waveforms which have different duty ratios, based on the lower 5 bits d0 through d4 of the 8-bit display data.
Accordingly, the 8-bit driving device 700 outputs signals t0 through t4 having waveforms shown in FIG. 29.
Table 4A shows a logical configuration of the interpolation signal generation circuit 731, and Table 4B shows a logical configuration of the voltage selection and modulation circuit 732.
TABLE 4A ______________________________________ d4 d3 d2 d1 d0 T ______________________________________ * * * * 1 .tau.0 * * * 1 * .tau.1 * * 1 * * .tau.2 * 1 * * * .tau.3 1 * * * * .tau.4 ______________________________________
Symbol * indicates that the memory data and the signal are not related to each other.
TABLE 4B __________________________________________________________________________ d7 d6 d5 S0 S32 S64 S96 S128 S160 S192 S224 S256 __________________________________________________________________________ 0 0 0 T T 0 0 1 T T 0 1 0 T T 0 1 1 T T 1 0 0 T T 1 0 1 T T 1 1 0 T T 1 1 1 T T __________________________________________________________________________
The interpolation signal T from the interpolation signal generation circuit 731 is expressed by: EQU T=d0.tau.0+d1.tau.1+d2.tau.2+d3.tau.3+d4.tau.4.
In this manner, 31 interpolation gray-scale voltages are formed between the nine reference gray-scale voltages. As a result, 256-gray-scale display is realized by the 8-bit driving device 700. Such an 8-bit driving device is proposed in Japanese Patent Application No. 5-297103.
However, the voltage to be supplied to the pixels changes for the same reason as described regarding the 3-bit driving device 500 and the 6-bit driving device 600.
In the case of 256-gray-scale display, the difference between voltages corresponding to two adjacent gray-scale levels is very small, and thus gray-scale inversion occurs by even a very slight change in the voltage.
For example, if a voltage corresponding to 256 gray-scale levels is equally divided within 5 volts, the voltage difference between two adjacent gray-scale levels is only approximately 20 mV. This is 1/4 the voltage difference of a 64-gray-scale display. If the voltage changes by 30 mV in the output circuit, no gray-scale inversion occurs in a 6-bit driving device, but gray-scale inversion occurs in an 8-bit driving device. Such an 8-bit driving device cannot be used for 256-gray-scale display. In practice, the voltage vs. transmittance curve of the liquid crystal material is nonlinear. Accordingly, the difference between voltages corresponding to two adjacent gray-scale levels in 256-gray-scale display is approximately 5 mV in an intermediate area of the gray scale between the highest gray-scale level and the lowest gray-scale level, which is much smaller than 20 mV. For 256-gray-scale display, a voltage change needs to be restricted to such extreme precision.
In the above-described conventional driving devices, interpolation gray-scale voltages are formed using reference gray-scale voltages supplied from outside the devices and a voltage corresponding to the display data is supplied to the load. For example, the interpolation gray-scale voltages are formed using adjacent three reference gray-scale voltages and supplied to the pixels. In a voltage supply line for supplying the intermediate reference gray-scale voltage, a voltage drop or a voltage rise which needs to occur is prevented due to the influence of the currents flowing to the load which is provided with the interpolation voltages interposing the intermediate reference gray-scale voltage. As a result, crosstalk occurs, and thus accurate reproduction of the display data is not realized.